34 #ifndef _RTE_ETH_CTRL_H_ 35 #define _RTE_ETH_CTRL_H_ 59 #define RTE_ETH_FLOW_UNKNOWN 0 60 #define RTE_ETH_FLOW_RAW 1 61 #define RTE_ETH_FLOW_IPV4 2 62 #define RTE_ETH_FLOW_FRAG_IPV4 3 63 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4 64 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5 65 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6 66 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7 67 #define RTE_ETH_FLOW_IPV6 8 68 #define RTE_ETH_FLOW_FRAG_IPV6 9 69 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10 70 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11 71 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12 72 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13 73 #define RTE_ETH_FLOW_L2_PAYLOAD 14 74 #define RTE_ETH_FLOW_IPV6_EX 15 75 #define RTE_ETH_FLOW_IPV6_TCP_EX 16 76 #define RTE_ETH_FLOW_IPV6_UDP_EX 17 77 #define RTE_ETH_FLOW_PORT 18 79 #define RTE_ETH_FLOW_VXLAN 19 80 #define RTE_ETH_FLOW_GENEVE 20 81 #define RTE_ETH_FLOW_NVGRE 21 82 #define RTE_ETH_FLOW_MAX 22 88 RTE_ETH_FILTER_NONE = 0,
89 RTE_ETH_FILTER_MACVLAN,
90 RTE_ETH_FILTER_ETHERTYPE,
91 RTE_ETH_FILTER_FLEXIBLE,
93 RTE_ETH_FILTER_NTUPLE,
94 RTE_ETH_FILTER_TUNNEL,
97 RTE_ETH_FILTER_L2_TUNNEL,
115 RTE_ETH_FILTER_OP_MAX
143 #define RTE_ETHTYPE_FLAGS_MAC 0x0001 144 #define RTE_ETHTYPE_FLAGS_DROP 0x0002 151 struct rte_eth_ethertype_filter { 158 #define RTE_FLEX_FILTER_MAXLEN 128 159 #define RTE_FLEX_FILTER_MASK_SIZE \ 160 (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT) 192 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001 193 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 194 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 195 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 196 #define RTE_NTUPLE_FLAGS_PROTO 0x0010 197 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 199 #define RTE_5TUPLE_FLAGS ( \ 200 RTE_NTUPLE_FLAGS_DST_IP | \ 201 RTE_NTUPLE_FLAGS_SRC_IP | \ 202 RTE_NTUPLE_FLAGS_DST_PORT | \ 203 RTE_NTUPLE_FLAGS_SRC_PORT | \ 204 RTE_NTUPLE_FLAGS_PROTO) 206 #define RTE_2TUPLE_FLAGS ( \ 207 RTE_NTUPLE_FLAGS_DST_PORT | \ 208 RTE_NTUPLE_FLAGS_PROTO) 210 #define TCP_URG_FLAG 0x20 211 #define TCP_ACK_FLAG 0x10 212 #define TCP_PSH_FLAG 0x08 213 #define TCP_RST_FLAG 0x04 214 #define TCP_SYN_FLAG 0x02 215 #define TCP_FIN_FLAG 0x01 216 #define TCP_FLAG_ALL 0x3F 248 RTE_TUNNEL_TYPE_NONE = 0,
249 RTE_TUNNEL_TYPE_VXLAN,
250 RTE_TUNNEL_TYPE_GENEVE,
251 RTE_TUNNEL_TYPE_TEREDO,
252 RTE_TUNNEL_TYPE_NVGRE,
253 RTE_TUNNEL_TYPE_IP_IN_GRE,
254 RTE_L2_TUNNEL_TYPE_E_TAG,
261 #define ETH_TUNNEL_FILTER_OMAC 0x01 262 #define ETH_TUNNEL_FILTER_OIP 0x02 263 #define ETH_TUNNEL_FILTER_TENID 0x04 264 #define ETH_TUNNEL_FILTER_IMAC 0x08 265 #define ETH_TUNNEL_FILTER_IVLAN 0x10 266 #define ETH_TUNNEL_FILTER_IIP 0x20 268 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \ 269 ETH_TUNNEL_FILTER_IVLAN) 270 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \ 271 ETH_TUNNEL_FILTER_IVLAN | \ 272 ETH_TUNNEL_FILTER_TENID) 273 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \ 274 ETH_TUNNEL_FILTER_TENID) 275 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \ 276 ETH_TUNNEL_FILTER_TENID | \ 277 ETH_TUNNEL_FILTER_IMAC) 300 uint32_t ipv6_addr[4];
313 RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
314 RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
315 RTE_ETH_GLOBAL_CFG_TYPE_MAX,
329 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 330 #define RTE_ETH_INSET_SIZE_MAX 128 335 enum rte_eth_input_set_field { 336 RTE_ETH_INPUT_SET_UNKNOWN = 0,
339 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
340 RTE_ETH_INPUT_SET_L2_DST_MAC,
341 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
342 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
343 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
346 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
347 RTE_ETH_INPUT_SET_L3_DST_IP4,
348 RTE_ETH_INPUT_SET_L3_SRC_IP6,
349 RTE_ETH_INPUT_SET_L3_DST_IP6,
350 RTE_ETH_INPUT_SET_L3_IP4_TOS,
351 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
352 RTE_ETH_INPUT_SET_L3_IP6_TC,
353 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
354 RTE_ETH_INPUT_SET_L3_IP4_TTL,
355 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
358 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
359 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
360 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
361 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
362 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
363 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
364 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
367 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
368 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
369 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
370 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
371 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
374 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
375 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
376 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
377 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
378 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
379 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
380 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
381 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
383 RTE_ETH_INPUT_SET_DEFAULT = 65533,
384 RTE_ETH_INPUT_SET_NONE = 65534,
385 RTE_ETH_INPUT_SET_MAX = 65535,
392 RTE_ETH_INPUT_SET_OP_UNKNOWN,
395 RTE_ETH_INPUT_SET_OP_MAX
506 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
507 RTE_FDIR_TUNNEL_TYPE_NVGRE,
508 RTE_FDIR_TUNNEL_TYPE_VXLAN,
566 RTE_ETH_FDIR_ACCEPT = 0,
568 RTE_ETH_FDIR_PASSTHRU,
634 RTE_ETH_PAYLOAD_UNKNOWN = 0,
639 RTE_ETH_PAYLOAD_MAX = 8,
689 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) 690 #define RTE_FLOW_MASK_ARRAY_SIZE \ 691 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) 708 uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
750 RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
753 RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
780 RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
787 RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
794 RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
797 RTE_ETH_HASH_FUNCTION_MAX,
800 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ 801 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) 814 uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
816 uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
#define RTE_ETH_FDIR_MAX_FLEXLEN
uint32_t flex_payload_unit
rte_eth_fdir_filter_info_type
#define RTE_FLEX_FILTER_MAXLEN
uint32_t max_flex_payload_segment_num
uint32_t max_flex_bitmask_num
uint32_t flex_bitmask_unit
enum rte_mac_filter_type filter_type
uint16_t flex_payload_limit
#define RTE_ETH_INSET_SIZE_MAX
uint8_t mac_addr_byte_mask
#define RTE_FLEX_FILTER_MASK_SIZE
rte_eth_hash_filter_info_type